1. Field of the Invention
The present invention is generally related to the field of manufacturing integrated circuit devices, and, more particularly, to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of various features of the integrated circuit devices, e.g., transistors, word lines, etc. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the features of a typical memory device to increase the overall speed and capabilities of the memory device, as well as electronic devices incorporating such memory devices.
A variety of semiconductor memory devices are used extensively in many consumer products. Illustrative examples of such memory devices are dynamic random access memory (DRAMs) and flash memory devices. FIG. 1A depicts an illustrative layout of a schematically depicted DRAM memory device 17 that is formed on a die 19 comprised of a semiconducting substrate 13. In general, the memory device 17 is comprised of a memory array 10 and a plurality of peripheral circuits 12. By way of example only, a plurality of schematically depicted illustrative peripheral circuits 12 are depicted in FIG. 1A. More specifically, the illustrative peripheral circuits 12 comprise read-write circuits 12A, sense amp circuits 12B and power management circuits 12C. Of course, the illustrative peripheral circuits depicted in FIG. 1A are not exhaustive of all such peripheral circuits 12 on the memory device 17. In general, the peripheral circuit 12 may comprise any circuitry on the memory device 17 other than the circuitry found within the memory array 10.
The memory array 17 includes a multitude of memory cells arranged in rows and columns. Each of the memory cells is structured for storing digital information in the form of a logical high (i.e., a “1”) or a logical low (i.e., a “0”). To write (i.e., store) a bit into a memory cell, a binary address having portions identifying the cell's row (the “row address”) and column (the “column address”) is provided to addressing circuitry in the memory device 17 to activate the cell, and bit is then supplied to the cell. Similarly, to read (i.e., retrieve) a bit from a memory cell, the cell is again activated using the cell's memory address and the bit is then output from the cell.
FIG. 1B is a cross-sectional view of a portion of the illustrative memory device 17 depicted in FIG. 1A. Depicted therein is an illustrative transistor 15, which is a portion of a peripheral circuit 12, and a plurality of word lines 11 within the memory array 10. Typically, the memory array 10 is much more densely packed than the peripheral circuits 12, i.e., the pitch between adjacent word lines 11 within the memory array 10 is typically much tighter than it is in the peripheral circuits 12. For example, the spacing 32 between adjacent features, i.e., word lines 11, in the memory array 10 may be approximately 50-90 nm, whereas the spacing between adjacent features, e.g., transistors 15 in the peripheral circuits 12, may be on the order of approximately 240-600 nm.
As indicated in FIG. 1B, the illustrative transistor 15 comprises a gate insulation layer 14, a gate electrode 16, a metal layer 18 and a cap layer 20 comprised of, for example, silicon nitride. The transistor 15 further comprises a plurality of source/drain regions 24 and a sidewall spacer 22. The word lines 11 within the memory array 10 also include a similar structure. The feature size 30 of the word lines 11 may be on the order of approximately 50-90 nm. Typically, the word lines 11 in the memory array 10 may have a pitch of approximately two times the feature size of the word lines 11. Thus, the spacing 32 between adjacent word lines 11 in the array 10 may be approximately equal to the feature size of the word line 11. A sidewall spacer 34 is also formed adjacent the word lines 11 depicted in FIG. 1B. Lastly, isolation regions 28 are formed in the substrate 13 as is well known in the art.
Typically, the sidewall spacers 22 on the peripheral circuits 12, as well as the sidewall spacers 34 formed in the memory array 10, are formed at the same time from the same layer of material. Thus, the thickness 26 of the spacers 22 formed in the peripheral circuits 12 is approximately the same as the thickness 36 of the spacers 34 formed within the memory array 10. Due to the densely packed nature of the word lines 11 in the memory array 10, the thickness of the spacers 22, 34 is limited by the size of a spacer that may be reliably formed in the very small spacing 32 between adjacent word lines 11. This is problematic in that, for a variety of reasons, it may be desirable to make the spacer 22 on the peripheral circuits 12 thicker than the spacer 34 within the memory array 10. For example, formation of the source/drain regions 24 of the transistors 15 in the peripheral circuits 12 generally involves an initial LDD implant, followed by the formation of spacers 22 and then followed by a source/drain implant step. However, given that the thickness 26 of the spacer 22 is constrained by the spacing 32 between the word lines 11 in the memory array 10, the source/drain regions 24 on the peripheral circuits 12 may not be located as precisely or formed as deep as they would otherwise be if the formation of the spacers 22 was independent of the formation of the spacers 34.
The present invention is directed to various methods and devices that may solve, or at least reduce, some or all of the aforementioned problems.